Apparatus of a digital echo canceller and method therefor
US6934385B2 · kind B2 · utility
0Cited by
7References
6Claims
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Key dates
| Filing date | Mar 19, 2001 |
| Grant date | Aug 23, 2005 |
| Priority date | — |
| Expiry date | Sep 22, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B3/23
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An apparatus of a digital echo canceller comprises a first-set delay circuits, a selector, a second-set delay circuits, a plurality of multipliers and an adder. The first-set delay circuits are arranged into groups, and each group has N delay circuits. An exhaustive search function is carried out to produce a plurality of energy sums. The selector will select the biggest energy sum to serve as a significant part and then transmit to the outputs of the second-set delay circuits, the multipliers and the adder. An estimated echo signal is produced to cancel the echo signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.