Virtual test environment
US6934670B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2001 |
| Grant date | Aug 23, 2005 |
| Priority date | — |
| Expiry date | Jun 17, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318364
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of and an apparatus for designing a test environment and of evaluating performance of the test environment and an electronic device during testing of the electronic device. A virtual test environment is created emulating an actual test environment. A virtual device emulating the actual electronic device is implanted into the virtual test environment, and that virtual device is stimulated with an input test signal emulating the actual input signal applied to the actual electronic device in the actual test environment. The integrity of the input test signal and the resulting output signal is evaluated. An adjustment might be made to the virtual calibration of the virtual test environment and/or to the virtual device, or both, and the design of the actual device might be improved. The invention can be implemented on a properly programmed general purpose processing system or on a special purpose system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.