Programmable counters for setting bus arbitration delays involves counting clock cycles equal to a count number loaded from a memory
US6934871B2 · kind B2 · utility
4Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 17, 2001 |
| Grant date | Aug 23, 2005 |
| Priority date | — |
| Expiry date | Jun 9, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0036
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for generating a delay in the timing of a bus or other logic circuit such that changes may be made to timing parameters without undue hardware design changes is disclosed. A counter is used to count a number of clock cycles to time the delay. The number of clock cycles is pre-loaded into the counter from a memory. This eliminates the need for costly hardware design changes when timing parameters change, since all that must be changed is the number of clock cycles to be counted, which can be modified by replacing or reprogramming the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.