Multi-channel, multi-service debug on a pipelined CPU architecture
US6934937B1 · kind B1 · utility
18Cited by
9References
31Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2000 |
| Grant date | Aug 23, 2005 |
| Priority date | — |
| Expiry date | Mar 30, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for debugging an executing service on a pipelined CPU architecture are described. In one embodiment, a breakpoint within an executing service is set and a minimum state of the executing service is saved. In addition, a program counter of the executing service is altered. The program counter is restored and the state of the executing service is restored.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.