Level shelter, semiconductor integrated circuit and information processing system
US6937065B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 5, 2003 |
| Grant date | Aug 30, 2005 |
| Priority date | — |
| Expiry date | Jun 5, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/012
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level shifter normally operates with low power consumption at a high operating frequency. The level shifter, including a first level shifter, which has transistors MP3 and MP4, which have a supply voltage VDD applied to respective sources and respective gates connected to the other's drain, and transistors MN3 and MN4, which have signals SIN and SINB applied to respective gates, respective drains connected to the transistors MP3 and MP4 drains, and respective sources grounded; and a second level shifter, which has transistors MN5 and MN6, which have respective sources grounded and respective drains connected to the other's gate, and transistors MP5 and MP6, which have a supply voltage VDD applied to respective sources, signals SIN and SINB applied to respective gates, and respective drains connected to the transistors MP5 and MP6 drains; wherein the drains of the transistors MP3 and MN5 are connected to each other, and the drains of the transistors MP4 and MN6 are connected to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.