Method and apparatus for reducing lock time in dual charge-pump phase-locked loops
US6937075B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 2003 |
| Grant date | Aug 30, 2005 |
| Priority date | — |
| Expiry date | May 29, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop includes a phase detector to measure a phase offset between a reference clock signal and a feedback clock signal, and to generate first and second output control signals having a pulse width corresponding to the phase offset. The phase locked loop further includes a first pulse width control circuit coupled to the phase detector to reduce the pulse width of the first output control signal producing a first modified output control signal, a second pulse width control circuit coupled to the phase detector to reduce the pulse width of the second output control signal producing a second modified output control signal, a first charge pump coupled to the phase detector to provide a first charge signal responsive to the first and second output control signals, and a second charge pump coupled to the first and second pulse width control circuits to provide a second charge signal responsive to the first and second modified output control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.