Built-in jitter measurement circuit for voltage controlled oscillator and phase locked loop
US6937106B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 2, 2004 |
| Grant date | Aug 30, 2005 |
| Priority date | — |
| Expiry date | Mar 6, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/06
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A built-in jitter measurement circuit for a VCO (voltage-controlled oscillator) and a PLL (phase-locked loop) is disclosed. The circuit includes a divider for dividing frequency of a signal, a time to digital converter (TDC) for converting the period of the divided signal into digital values, a variance calculator for calculating variance of the period of the divided signal, a mean calculator for calculating mean value of the period of the divided signal, a encoder and counter for encoding and calculating the period of the divided signal, and a state controller as a controller for all other components. The circuit disclosed utilizes output clock of an opened-loop circuit to be measured and a divider for increasing jitter of the original signal. By measuring the bandwidth of a closed-loop circuit, accordingly, jitter of output clock of an opened-loop or an closed-loop circuit is measured by correlating the measured bandwidth and the jitter values from extrapolation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.