Method and apparatus using the Bresenham algorithm to synthesize a composite SYNC signal
US6937290B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2001 |
| Grant date | Aug 30, 2005 |
| Priority date | — |
| Expiry date | Aug 16, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N5/06
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit for generating a train of synthesized sync pulses in accordance with the Bresenham algorithm in response to an input clock having frequency Fi, such that the leading edges of the pulses occur at least nearly periodically, with time-averaged frequency at least nearly equal to (A/T)Fi, where A and T are integers, and such that the accumulated error, between the actual time interval between the first and last leading edges of Z consecutive ones of the pulses and the time ZT/(AFi), never exceeds 1/Fi. When Fi is equal to (T/A)Fo, where Fo is a predetermined output line frequency, an embodiment of the sync pulse generator includes an accumulator which stores a Count value, a comparator, and logic circuitry for generating the sync pulse train in response to a binary signal asserted by the comparator (and typically also control data that determines a configuration of the logic circuitry). The Count value is set to zero in response to a Frame Start event, and then increases by the above-noted integer value, A, once per input clock cycle. During each input clock cycle, the comparator compares the Count value in the accumulator with the above-noted integer value, T. In r…
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