Memory module, memory chip, and memory system
US6937494B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2003 |
| Grant date | Aug 30, 2005 |
| Priority date | — |
| Expiry date | Oct 31, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory module includes at least one CAR and a plurality of DRAMs provided so as to be close and adjacent to one another on one face and the other face of a module substrate. The DRAMs are divided into a plurality of memory groups. Memory groups adjacent to each other of these memory groups are paired with each other. One of this pair is a 1-ranked memory group and the other is a 2-ranked memory group. This pair of the memory groups is connected to the CAR via short wiring with a T-branch structure having a short stub. One of the pair of the memory groups on the signal-reception side functions as an open end. Active termination is performed by a termination resistor of the other of the pair of the memory groups on the signal-non-reception side. Subsequently, signal reflections can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.