Data structures for efficient processing of IP fragmentation and reassembly
US6937606B2 · kind B2 · utility
81Cited by
8References
12Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 20, 2001 |
| Grant date | Aug 30, 2005 |
| Priority date | — |
| Expiry date | Aug 19, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/22
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Data structures, a method, and an associated transmission system for IP fragmentation and IP reassembly on network processors in order to minimize memory allocation requirements. Frame data for IP fragmentation or reassembly on a network processor is read into buffers to which are associated various control structures. The control structures permit IP fragmentation or reassembly to be accomplished without creating multiple copies of the frame or fragments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.