Cache-line reuse-buffer
US6938126B2 · kind B2 · utility
4Cited by
17References
34Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2002 |
| Grant date | Aug 30, 2005 |
| Priority date | — |
| Expiry date | Mar 6, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, apparatus, and system that compares a current fetch request having a first start address and length associated with the current fetch request to a second start address of the next fetch request, determines whether the content already loaded in a buffer will be used to at least partially fulfill the next fetch request based upon the comparison, and inhibits access to an instruction cache based upon the comparison.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.