Node processors for use in parity check decoders
US6938196B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2002 |
| Grant date | Aug 30, 2005 |
| Priority date | — |
| Expiry date | Feb 21, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6583
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Techniques for implementing message passing decoders, e.g., LDPC decoders, are described. To facilitate hardware implementation messages are quantized to integer multiples of ½ ln2. Messages are transformed between more compact variable and less compact constraint node message representation formats. The variable node message format allows variable node message operations to be performed through simple additions and subtractions while the constraint node representation allows constraint node message processing to be performed through simple additions and subtractions. Variable and constraint nodes are implemented using an accumulator module, subtractor module and delay pipeline. The accumulator module generates an accumulated message sum. The accumulated message sum for a node is stored and then delayed input messages from the delay pipeline are subtracted there from to generate output messages. The delay pipeline includes a variable delay element making it possible to sequentially perform processing operations corresponding to nodes of different degrees.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.