Method and apparatus for designing semiconductor integrated circuit device based on voltage drop distribution
US6938233B2 · kind B2 · utility
8Cited by
6References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2003 |
| Grant date | Aug 30, 2005 |
| Priority date | — |
| Expiry date | Aug 8, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for designing a semiconductor integrated circuit device for connecting between terminals of transistors formed on a silicon wafer by metal wiring. The method includes a first step of carrying out a schematic arrangement so as to minimize a distance of a wiring for connecting between the transistors or wiring capacitance based on input information on transistors; a second step of producing information on a voltage drop value based on the schematic arrangement of the transistors; and a third step of arranging the transistors based on the information on a voltage drop value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.