Semiconductor memory cell

US6940121B2 · kind B2 · utility

Assignee

• Infineon Technology AG · DE

Inventor

• Oliver Gehring · Dresden, DE

Key dates

• Filing date: Sep 19, 2001
• Grant date: Sep 6, 2005
• Expiry date: Sep 19, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/681

Abstract

A semiconductor memory cell includes a semiconductor substrate that defines a trench having trench walls. The semiconductor memory cell also includes a floating gate electrode positioned within the trench and insulated from the trench walls by a first insulation region; a control gate electrode surrounding the trench; and a second insulation layer on the surface of the semiconductor substrate. The semiconductor memory cell further includes a conductive layer positioned on the second insulation layer. The conductive layer includes a channel region positioned above the floating gate electrode. The semiconductor memory cell also includes a source region and a drain region. The source region and the drain region are each formed in the conductive layer. The source region and the drain region are also connected to the channel region.