System architecture for scan line non-linearity compensation in a ROS system
US6940536B2 · kind B2 · utility
12Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2002 |
| Grant date | Sep 6, 2005 |
| Priority date | — |
| Expiry date | Apr 29, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N2201/04793
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A system architecture for scanned non-linearity correction in a printer uses any raster output scanner having scanned non-linearity profile previously stored in memory from a test station installed with any pixel board. The pixel board includes a correction table register wherein the pixel board utilizes the scanned non-linearity profile of the raster output scanner to calculate the correction table register to correct for pixel misregistration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.