Liquid crystal displays including organic passivation layer contacting a portion of the semiconductor layer between source and drain regions
US6940566B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2003 |
| Grant date | Sep 6, 2005 |
| Priority date | — |
| Expiry date | Oct 4, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/136209
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A passivation layer is formed by coating a flowable insulating material on the substrate where a thin film transistor and a storage capacitor electrode, and a pixel electrode is formed on the passivation layer. A portion of the passivation layer is etched using the pixel electrode as a mask to make a groove on the thin film transistor, and then a black matrix is formed by filling an organic black photoresist in the groove. To increase the storage capacitance, a portion of the passivation layer is removed or to form a metal pattern on the storage capacitor electrode. A flowable insulating material is used as a gate insulating layer to planarize the substrate. In this case of the etch stopper type thin film transistor, a photo definable material is used as the etch stopper layer to reduce the parasitic capacitance between the gate electrode and the drain electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.