Semiconductor memory devices for outputting bit cell data without separate reference voltage generator and related methods of outputting bit cell data
US6940743B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 9, 2004 |
| Grant date | Sep 6, 2005 |
| Priority date | — |
| Expiry date | Jun 9, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4099
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Semiconductor memory devices are provided which include an array of memory cells, an array of reference cells, and a plurality of sense amplifiers that are associated with respective of the memory cells. The reference cells have a first capacitor that is coupled to a first supply voltage, to a first complementary bit line associated with one of the memory cells and to a second complementary bit line that is associated with a different memory cell. The sense amplifiers are configured to sense and amplify the voltage difference between a signal on the first bit line and a signal on the first complementary bit line. These semiconductor memory devices may output bit cell data without a separate reference voltage generator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.