Scheduling the dispatch of cells in non-empty virtual output queues of multistage switches using a pipelined arbitration scheme
US6940851B2 · kind B2 · utility
22Cited by
3References
26Claims
0Family size
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Key dates
| Filing date | Jul 23, 2001 |
| Grant date | Sep 6, 2005 |
| Priority date | — |
| Expiry date | Feb 7, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5681
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A pipeline-based matching scheduling approach for input-buffered switches relaxes the timing constraint for arbitration with matching schemes, such as CRRD and CMSD. In the new approach, arbitration may operate in a pipelined manner. Each sub-scheduler is allowed to take more than one time slot for its matching. Every time slot, one of them provides a matching result(s). The sub-scheduler can use a matching scheme such as CRRD and CMSD.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.