Buffer switch having descriptor cache and method thereof
US6941392B2 · kind B2 · utility
4Cited by
21References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2004 |
| Grant date | Sep 6, 2005 |
| Priority date | — |
| Expiry date | Apr 28, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/3036
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A buffer switch comprises a data memory that stores a plurality of data. A cache memory comprises a plurality of FIFO mini-queues each storing a plurality of descriptors each corresponding to a respective one of the plurality of data. An output memory comprises a plurality of output queues. A burst writer simultaneously transfers M ones of the plurality of descriptors stored in a corresponding one of the plurality of mini-queues to at least a corresponding one of the plurality of output queues. The burst writer accesses the output memory, when the output memory is available, once for every M ones of the plurality of descriptors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.