Processing method, chip set and controller for supporting message signaled interrupt
US6941398B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2001 |
| Grant date | Sep 6, 2005 |
| Priority date | — |
| Expiry date | Mar 16, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/2418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing method, a chip set and a controller for supporting message signaled interrupt. A memory write transaction on a PCI bus is monitored. When the address of the system memory specified in the interrupt message of the write transaction is located at a range of a reserved interrupt address, the interrupting service sequence is performed. The reserved interrupt address is located in an address of a system memory. Thus, the data to be processed and the system-specified message are written in the buffer and arranged in sequence. The problem of “write buffer latency” is resolved, and is irrelevant to the level of the PCI bus. Many system specified messages can be stored in the system memory, so that multiple system message signaled interrupts issue from different peripheral components can be processed in the same interrupt service routine.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.