System for head and tail caching
US6941426B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 31, 2001 |
| Grant date | Sep 6, 2005 |
| Priority date | — |
| Expiry date | Apr 13, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/108
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A head and tail caching system. The system includes a tail FIFO memory having a tail input to receive incoming data. A memory is included that is operable to store data that is output from the tail FIFO and output the stored data at a memory output. A multiplexer is included having first and second multiplexer inputs coupled to the tail FIFO and the memory, respectively. The multiplexer has a control input to select one of the multiplexer inputs to coupled to a multiplexer output. A head FIFO memory receives data from the multiplexer output, and outputs the data on an output data path. A controller is operable to transfer one or more blocks data having a selected block size from the tail FIFO to the memory and from the memory to the head FIFO, to achieve a selected efficiency level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.