Memory controller optimization
US6941428B2 · kind B2 · utility
11Cited by
21References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 25, 2002 |
| Grant date | Sep 6, 2005 |
| Priority date | — |
| Expiry date | May 22, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1626
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller, method and program product for memory controller optimization by active re-prioritization of requests based on memory bus activity. The invention continually monitors memory bus activity and, where necessary, re-prioritizes a queue of pending memory requests. In addition, mechanisms are provided to abort an existing request on a memory bus, and interrupt an existing request to complete a pending request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.