Systems and methods for memory read response latency detection
US6941433B1 · kind B1 · utility
54Cited by
6References
28Claims
0Family size
Assignee
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Key dates
| Filing date | May 22, 2002 |
| Grant date | Sep 6, 2005 |
| Priority date | — |
| Expiry date | Jul 24, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4239
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for determining a memory read latency includes a memory, a memory read circuit, and a latency detector. An identifiable pattern of data is written to at least one location in the memory, and a read request and the address of the identified pattern are sent to the memory. The latency detector determines a read latency period based on detecting the identifiable pattern of data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.