Method and apparatus for transitioning a processor state from a first performance mode to a second performance mode
US6941480B1 · kind B1 · utility
55Cited by
22References
13Claims
0Family size
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Key dates
| Filing date | Sep 30, 2000 |
| Grant date | Sep 6, 2005 |
| Priority date | — |
| Expiry date | Sep 25, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and an apparatus to dynamically transition a processor between two performance states, high performance and low power. Predetermined core clock frequency and supply voltage levels of the processor define each performance state. Transitioning the supply voltage while the processor is in the active mode and transitioning the frequency while the processor is in the sleep mode significantly reduce the processor latency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.