Memory subsystem including an error detection mechanism for address and control signals
US6941493B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 27, 2002 |
| Grant date | Sep 6, 2005 |
| Priority date | — |
| Expiry date | Apr 12, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1044
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory subsystem includes a memory controller coupled to a memory module including a plurality of memory chips via a memory bus. The memory controller may generate a plurality of memory requests each including address information and corresponding error detection information. The corresponding error detection information is dependent upon said address information. The memory module may receive each of the plurality of memory requests. An error detection circuit within the memory module may detect an error the address information based upon the corresponding error detection information and may provide an error indication in response to detecting the error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.