Built-in test for multiple memory circuits
US6941494B1 · kind B1 · utility
14Cited by
7References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2001 |
| Grant date | Sep 6, 2005 |
| Priority date | — |
| Expiry date | Aug 1, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory test circuit includes a collar for coupling to a memory device for switching an address bus and a data bus of the memory device between an external circuit and the collar in response to a switching signal; and a controller coupled to the collar for generating the switching signal, a test vector, and control signals between the controller and the collar on as few as seven control lines for testing the memory device with the test vector. Multiple memory devices of various sizes may be tested with the same controller concurrently.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.