Method of cross-mapping integrated circuit design formats
US6941530B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2003 |
| Grant date | Sep 6, 2005 |
| Priority date | — |
| Expiry date | Jun 10, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of cross-mapping integrated circuit (“IC”) elements nets in a IC and/or directing a probe to points on an IC to achieve minimal interference from adjacent structures is disclosed. The method of provides a more streamlined approach than referencing points from a physical layout representation of the IC to the actual IC being tested. The improved correlation between the actual packaged IC and the layout of the IC is accomplished using artificial locator cells. Preferably, the artificial locator cells are generated from mathematical operations of the extracted version of the layout, and they further provide coordinate information for where minimal interference from adjacent structures may be accomplished. Artificial locator cells may be generated from a layout representing a hierarchical representation or alternately each element that is instantiated from a reference library may already have artificial locator cells included.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.