Automatic instruction set architecture generation
US6941548B2 · kind B2 · utility
10Cited by
12References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2001 |
| Grant date | Sep 6, 2005 |
| Priority date | — |
| Expiry date | Mar 8, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/443
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital computer system automatically creates an Instruction Set Architecture (ISA) that potentially exploits VLIW instructions, vector operations, fused operations, and specialized operations with the goal of increasing the performance of a set of applications while keeping hardware cost below a designer specified limit, or with the goal of minimizing hardware cost given a required level of performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.