Method for fabricating integrated circuit package with solder bumps
US6943060B1 · kind B1 · utility
2Cited by
7References
25Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 5, 2004 |
| Grant date | Sep 13, 2005 |
| Priority date | — |
| Expiry date | Mar 5, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package with solder bumps and a method for making the same are described. One embodiment comprises a flip-chip design with a rectangular semiconductor die with a relatively large aspect ratio bonded to a substantially square substrate through solder bumps. In one embodiment, active bumps are concentrated in an area relatively close to the neutral point of the die, for example, in a substantially square area about the neutral point.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.