Packaging system for power supplies
US6943455B1 · kind B1 · utility
12Cited by
6References
30Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 27, 2003 |
| Grant date | Sep 13, 2005 |
| Priority date | — |
| Expiry date | Apr 30, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaging system for a high current, low voltage power supply. The power supply uses two bare die field effect transistors whose input and output electrodes are solder attached to low resistance, high current posts in the package. An associated controller chip is mounted to a rigid circuit board, and the circuit board is mechanically attached to the posts. The circuit board thereby gives physical rigidity to the package, but carries no high currents. The use of low resistance, high current posts reduces the heat generated, improving the long term reliability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.