Delay-compensated fractional-N frequency synthesizer
US6943600B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 16, 2003 |
| Grant date | Sep 13, 2005 |
| Priority date | — |
| Expiry date | Feb 6, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1976
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A Phase-Locked Loop is provided that includes a main loop, a calibration loop, and Control Logic. The main loop comprises, coupled in series, a Phase Frequency Detector, a Main Charge Pump, a Main Loop Filter, a Voltage Controlled Oscillator and a Frequency Divider. The calibration loop is coupled to the Phase Frequency Detector and comprises a Calibration Charge Pump and a Calibration Loop Filter. The Control Logic controls the Frequency Divider and receives a control input signal. A Reference Frequency Signal is coupled to the Phase Frequency Detector and the Control Logic, and a calibration signal is coupled to the calibration loop. Additionally, the main loop further comprises a delay generator controlled by the Control Logic and arranged to receive correction signals from the calibration loop and to send an output signal to the Phase Frequency Detector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.