Process and device for the sequential addressing of the inputs of a multiplexer of a data acquisition circuit
US6943713B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2000 |
| Grant date | Sep 13, 2005 |
| Priority date | — |
| Expiry date | Mar 10, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG08C15/00
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The systematic, and possibly repeated, acquisition of several distinct quantities for exploitation by a user system by utilizing a multiplexer with staged architecture without all inputs hard-wired. Each multiplexer stage is addressed by an elementary counter chained with elementary counters for addressing lower stages. The multiplexer inputs are scanned by regularly incrementing the chain of counters. If no precaution is taken, all the multiplexer inputs are scanned without considering their possible absences. To remedy this drawback a first elementary counter addresses the first stage of adjustable counting capacity switches, the elementary counters can address intermediate stages of the switches with controllable shunting circuits, and a global counter is reconfigured, at the end of each counting cycle of the first elementary counter, by commands adjusting the first elementary counter capacity, and activating or inhibiting the shunting circuits. The stored commands are a string of instructions executed one by one.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.