Early primitive assembly and screen-space culling for multiple chip graphics system
US6943797B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2003 |
| Grant date | Sep 13, 2005 |
| Priority date | — |
| Expiry date | Aug 21, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/80
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A multi-chip system and method are disclosed for incorporating a primitive assembler in each of one or more geometry chips and one or more rasterization chips. This system may allow per-primitive operations to be performed in the geometry chips, and also allow use of a vertex data interface for sending vertex data to the rasterization chips. The primitive assemblers in the geometry chips may assemble vertices into primitives for clipping tests. The geometry chips may also test an assembled primitive against the projected boundaries of a set of screen space regions, where each region is assigned to one of the rasterization chips. Those primitives residing in more than one region may be sub-divided into two or more new primitives so that each new primitive resides in only one screen space region. The geometry chip may then send the vertex data for each primitive to the corresponding rasterization chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.