Multi-pair transceiver decoder system with low computation slicer
US6944237B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2002 |
| Grant date | Sep 13, 2005 |
| Priority date | — |
| Expiry date | Jan 3, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03745
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and a system for decoding information signals encoded by a multi-state encoding architecture and transmitted over a multi-dimensional transmission channel by computing a distance of a received word from a codeword. One-dimensional (1D) input signals are detected in a symbol decoder, implemented using look-up tables, to produce a pair of 1D errors, with each representing a distance metric between the input signal and a symbol in one of two disjoint symbol-subsets. The symbol decoder is implemented as a pair of slicers, each detecting an input signal with respect to one of two disjoint symbol-subsets. A third slicer detects the input with respect to the union of the two disjoint symbol-subsets. Decisions from the first, second and third slicers are processed to define 1D square error terms expressed in Hamming metrics. Reduced bit count error terms allow follow-on error processing to be performed with a minimum of computational complexity. The 1D errors are combined to produce a set of multi-dimensional error terms. Each of the multi-dimensional error terms corresponds to a distance between a received word and a nearest codeword.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.