Architecture that converts a half-duplex bus to a full-duplex bus while keeping the bandwidth of the bus constant
US6944691B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2001 |
| Grant date | Sep 13, 2005 |
| Priority date | — |
| Expiry date | Jun 14, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4009
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An architecture comprising a first circuit, a second circuit, and one or more pairs of communication channels. The first circuit may be configured to transmit one or more first serial streams in response to a plurality of first source data streams and recover a plurality of second source data streams from one or more second serial streams. The second circuit may be configured to transmit the one or more second serial streams in response to the plurality of second source data streams and recover the plurality of first source data streams in response to the one or more first serial streams. The first circuit and the second circuit may be coupled by the one or more pairs of communication channels. The first and second circuits may be configured to transmit simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.