Managing latencies in accessing memory of computer systems
US6944736B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2002 |
| Grant date | Sep 13, 2005 |
| Priority date | — |
| Expiry date | Dec 23, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4881
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention, in various embodiments, provides techniques for managing latencies in accessing memory of computer systems. In one embodiment, upon accessing the memory system for a piece of data used by a first process, a latency manager determines the access time to acquire the piece of data in the memory system. The latency manager then compares the determined access time to a threshold. If the determined access time is greater than the threshold, the latency manager triggers an interrupt for the operating system to switch threads or processes so that execution of the first process is postponed and execution of a second process starts. Various embodiments include the latency manager is polled for the access time when the processor is stalled, the latency manager triggers a process switch when a particular memory subsystem is accessed, etc.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.