Memory modules and methods having a buffer clock that operates at different clock frequencies according to the operating mode
US6944737B2 · kind B2 · utility
14Cited by
7References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2002 |
| Grant date | Sep 13, 2005 |
| Priority date | — |
| Expiry date | Apr 16, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory modules and methods of testing memory modules are provided that include at least one memory device responsive to a memory clock signal having a memory clock frequency and a data buffer. The data buffer is responsive to a buffer clock signal having a first buffer clock frequency that is different from the memory clock frequency during a normal mode of operation and having a second buffer clock frequency that is equal to the memory clock frequency during a test mode of operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.