Production method for semiconductor device
US6946385B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 2, 2003 |
| Grant date | Sep 20, 2005 |
| Priority date | — |
| Expiry date | Jul 2, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/942
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a production method of a semiconductor device having multilayer interconnections of well-formed dual damascene structure in the low dielectric constant interlayer insulating film.The method includes a step of forming on an underlayer wiring a first insulating film, a second insulating, and first mask forming layer; a step of forming a first resist mask (20) having an inverted pattern of wiring trenches for the upper wiring; a step of etching the first mask forming layer through the first resist mask, thereby forming in the first mask forming layer a concave part conforming to the inverted pattern of wiring trenches for the upper wiring, and then forming on the first mask forming layer a second mask forming layer, thereby filling the concave part with the second mask forming layer; a step of selectively removing the second mask forming layer on the region in which the wiring trench is formed, thereby forming the second mask having the wiring trench pattern; a step of forming on the first mask forming layer a second resist mask (12) having an opening pattern of the via holes; a step of etching the first mask forming layer and the second insulating film through the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.