Differential sampling circuit for generating a differential input signal DC offset
US6946986B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2003 |
| Grant date | Sep 20, 2005 |
| Priority date | — |
| Expiry date | Dec 17, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A differential sampling circuit is configured around a differential operational amplifier and is provided with a pair of switched-capacitor networks, each including an circuit block, to generate the real value of the differential input signal DC offset at each system clock cycle. During the first half cycle, the differential input signal pair (Vin+,Vin−) is sampled and the holding capacitors in each network are charged. During the second half cycle, the differential input signal pair is sampled again and the holding capacitors are further charged. At the end of the cycle, the charges held in the holding capacitors are applied to the differential operational amplifier, so that the differential output signal is equal to the real differential input signal DC offset value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.