System and method for high-speed decoding and ISI compensation in a multi-pair transceiver system
US6947482B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2001 |
| Grant date | Sep 20, 2005 |
| Priority date | — |
| Expiry date | May 28, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03745
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and a system for providing ISI compensation to an input signal in a bifurcated manner. ISI compensation is provided in two stages, a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel. First stage ISI compensation is performed in an inverse response filter having a characteristic feedback gain factor K, during system start-up. Second stage ISI compensation is performed by a single DFE in combination with a MDFE operating on tentative decisions output from a Viterbi decoder. As the DFE of the second stage reaches convergence, the feedback gain factor K of the first stage is ramped to zero.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.