FIFO memory system and method
US6948030B1 · kind B1 · utility
5Cited by
26References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2002 |
| Grant date | Sep 20, 2005 |
| Priority date | — |
| Expiry date | Feb 13, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A FIFO memory system for multiple input channels, has a channel control logic coupled to a channel input signal. A pointer and flag logic block is coupled to an output of the channel control logic. A memory has an address bus coupled to the channel control logic and the pointer and flag logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.