Method and apparatus for reducing the effects of hot spots in cache memories
US6948032B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2003 |
| Grant date | Sep 20, 2005 |
| Priority date | — |
| Expiry date | Mar 14, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention provides a system that uses a hot spot cache to alleviate the performance problems caused by hot spots in cache memories, wherein the hot spot cache stores lines that are evicted from hot spots in the cache. Upon receiving a memory operation at the cache, the system performs a lookup for the memory operation in both the cache and the hot spot cache in parallel. If the memory operation is a read operation that causes a miss in the cache and a hit in the hot spot cache, the system reads a data line for the read operation from the hot spot cache, writes the data line to the cache, performs the read operation on the data line in the cache, and then evicts the data line from the hot spot cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.