High integrity recovery from multi-bit data failures
US6948091B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 2002 |
| Grant date | Sep 20, 2005 |
| Priority date | — |
| Expiry date | Oct 13, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1679
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Methods and system for facilitating a computing platform to recover quickly from transient multi-bit data failures within a run-time data memory array in a manner that is transparent to software applications executing on the computing platform. A fault-tolerant digital computing system is provided for that utilizes parallel processing lanes in a lockstep architecture. Each processing lane includes error detectors that are configured to detect multi-bit data errors in each processing lane's memory arrays. Upon detection of a multi-bit data failure, an interrupt is generated wherein control logic software responds to the interrupt and corrects the data errors in the memory array of each processing lane.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.