Circuits and methods for debugging an embedded processor and systems using the same
US6948098B2 · kind B2 · utility
57Cited by
14References
18Claims
0Family size
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Key dates
| Filing date | Mar 30, 2001 |
| Grant date | Sep 20, 2005 |
| Priority date | — |
| Expiry date | Oct 25, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31705
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A debugging subsystem for testing a system-on-a-chip includes an embedded processor and memory and includes at least one debugging subblock monitors a bus between the processor and the memory to detect selected triggering events, counts the number of triggering events detected and when the number of triggering events reaches a predetermined threshold, generates a debugging signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.