Retargetable compiling system and method
US6948158B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2001 |
| Grant date | Sep 20, 2005 |
| Priority date | — |
| Expiry date | Jun 27, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/47
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a compiling method and system for generating a sequence of program instructions for use in a processing architecture with architecture resources executing instructions from a corresponding instruction set. A retargetable compiler is used to generate a code using at least two instruction sets in the same processing architecture. One instruction set for a compact code and one for a parallel high performance code. The compact instruction set (Compact Instruction Format) covers a subset (RF11, ALU1, L/S1, BU1) of the architecture, whereas the complete instruction set covers the entire architecture (RF1, UC1, UC2, RF2, UC3, UC4, RF3, UC5, UC6, RF4, UC7). By using the at least two instruction sets of different sizes, the compiler is able to reduce the processed average code length, since fewer bits are needed in the compact code to encode operations and registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.