General purpose delay logic
US6949956B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 3, 2003 |
| Grant date | Sep 27, 2005 |
| Priority date | — |
| Expiry date | Oct 14, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00241
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A logic circuit for delaying a signal input thereto a specified number of clock cycles X, wherein X is between 1 and 2N is described. In one embodiment, the logic circuit comprises a demultiplexer (“DEMUX”) comprising an input for receiving the signal and N outputs; a register array comprising 2N clocked registers, wherein each of a first N of the clocked registers is connected to one of the N outputs of the DEMUX and wherein data is shifted out of one clocked register to a next clocked register on each clock cycle; and a multiplexer (“MUX”) comprising M inputs, wherein each of the M inputs is connected to one of the clocked registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.