Phase comparator capable of tolerating a non-50% duty-cycle clocks
US6949958B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2002 |
| Grant date | Sep 27, 2005 |
| Priority date | — |
| Expiry date | Oct 18, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.