Power consumption management in a video graphics accelerator
US6950105B2 · kind B2 · utility
33Cited by
8References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2002 |
| Grant date | Sep 27, 2005 |
| Priority date | — |
| Expiry date | Jul 23, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus matches one or more clock speeds used in, or used by, a graphics accelerator so as to match graphics processing requirements to the speed of the clock source or sources. Clock speed is adjusted under software control to match current requirements. Power is conserved by reducing clock speeds from unnecessarily high rates to a rate that can satisfy current display mode settings and other graphics processing demands.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.