Simultaneous access and reset system for an active pixel sensor
US6950131B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2000 |
| Grant date | Sep 27, 2005 |
| Priority date | — |
| Expiry date | Nov 9, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/766
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip for forming an electronic image in a digital camera includes an offset canceling column buffer for use with active pixel sensors having a small electrical buffer amplifier within each pixel The active pixel sensors are arranged on a semiconductor chip with simultaneous access and reset lines. Each active pixel sensor includes an source follower current amplifier, which introduces small variations in offset voltage, causing pattern noise to be introduced into the output signal of the sensed image. A method and apparatus is disclosed for addressing an array of active pixel sensors in a sequence coordinated with a column buffer for canceling pattern noise. To cancel pattern noise, the current row N in the APS cell array is accessed and sampled. Next, the following row N+1 is accessed thereby resetting the current row. Finally, the previous row N in the APS cell array is accessed a second time and sampled. Stored samples from the prior row N are subtracted from the previously sampled signals of the same prior row N to provide an output pixel signal value for which the APS offset voltage (pattern noise) is cancelled. In addition, accessing a row of the APS cell arra…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.