Method and a processor for processing two digital video signals clocked by respective clock signals of identical frequency but with a constant phase shift therebetween
US6950150B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2002 |
| Grant date | Sep 27, 2005 |
| Priority date | — |
| Expiry date | Nov 26, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/440218
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method and a processor for processing two digital video signals clocked by respective clock signals of identical frequency but with a constant phase shift therebetween. Standard definition and progressive scan digital video signals which are clocked at first and second clock signals CLOCK—1 and CLOCK—2, respectively, of identical frequency with a constant phase shift therebetween are interfaced with a processing circuit (7) by an interface circuit (10). The progressive scan signal is clocked into a first register (20) on the second clock signal CLOCK—2, and is clocked to a second register (21) by the first clock signal CLOCK—1 and in turn to a third register (22) by the first clock signal CLOCK—1. The edge of the first clock signal CLOCK—1 on which the progressive scan signal is clocked into the second register (21) is chosen to allow sufficient time to clock the signal. The standard definition signal is clocked through fourth, fifth and sixth registers (23, 24, 25), respectively, and both signals are clocked from the third and sixth registers (22, 25) on the first clock signal CLOCK—1 into the processing circuit (7).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.